1. Field of the Invention
The present invention relates generally to the field of semiconductor fabrication and, more particularly, to an improved semiconductor device structure with multi-layer contact etch stop layer (CESL) structure for reducing charging damage to integrated circuits during semiconductor manufacturing.
2. Description of the Prior Art
As known in the art, plasma process induced damage is caused by the accumulation of charges collected by floating conductors which act like antennas during a plasma processes. Typically, damage to thin insulators such as gate oxide sandwiched between a conductive substrate and isolated conductive electrodes on the surface of a wafer (gates) occurs due to current flow through the insulator, driven by a potential difference between the surface electrode and the substrate. During wafer processing, wafer-scale potential differences are caused by global non-uniformities in plasma density and/or electron temperature.
For the thick oxide devices, as the gate oxide thickness is large, there is not much leakage current through tunneling. This enables buildup of the charge at the gate electrode, raising its potential and finally breaking down the oxide or dielectric stack. In some cases, it could be a “hard” breakdown which render the device useless, while some other times it can create latent defects in the gate oxide stack which limits the lifetime of the device.
Charging damage to integrated circuits during plasma processing of integrated circuit die in a semiconductor wafer may be reduced by processing scribe lines during wafer fabrication to facilitate the flow of current to and from the wafer substrate through the scribe lines during integrated circuit fabrication and reduce current flow through integrated circuit components. However, the aforesaid prior art method is still not satisfactory.
In light of the above, plasma process induced damage is costly in terms of wafer yield and reliability, and therefore there is a need in the semiconductor processing art to develop an improved semiconductor device structure which is capable of overcoming the shortcomings and deficiencies of the prior art.